1. Field of the Invention
The present invention relates to a memory device which is accessible in parallel at a high speed by a single accessing operation.
2. Description of the Prior Art
Neighborhood operations and line tracing processes such as a spatial filtering in image processing frequently refer to peripheral pixels surrounding a pixel in question among image data stored in two-dimensional image memories. In this case, an eight-neighborhood operation with respect to the pixel in question is generally used.
When such an operation is carried out for "n.sub.1 .times.n.sub.2 " pixels by using a two-dimensional memory where only one pixel is accessible by a single memory accessing operation, the accessing operation is repeated "n.sub.1 .times.n.sub.2 " times for processing the "n.sub.1 .times.n.sub.2 " pixels, increasing the processing time.
To cope with this problem, there has been proposed a method using a high-speed memory device that has a quicker accessing speed than the processor. Within one memory accessing interval of the processor, the high-speed memory device accesses "n.sub.1 .times.n.sub.2 " pixels in time-dividing manner.
This high-speed memory device is, however, expensive and requires a controlling mechanism to be provided therewith for the time-sharing accessing, thereby increasing the cost and complicating the device.
There has been proposed another method to cope with the problem. This method uses, instead of the high-speed memory device, two-dimensional memories each having a normal accessing speed, the number of memories being "n.sub.1 .times.n.sub.2 " which corresponds to the total number of pixels. The respective two-dimensional memories store the pixels shifted one by one. Addresses respectively shifted one by one are simultaneously supplied to the respective two-dimensional memories such that the "n.sub.1 .times.n.sub.2 " pixels are simultaneously read by a single accessing operation.
However, this method requires the two-dimensional memories of the number of "n.sub.1 .times.n.sub.2 " so that the size of the memory device is large, increasing the cost. In addition, it is necessary in a writing operation to renew the same pixels of all of the "n.sub.1 .times.n.sub.2 " memories so that the respective two-dimensional memories should be supplied with the same addresses in the reading and writing operations. For this, an address switching mechanism should be added to the memory device, complicating the device. Although the reading operation may quickly be carried out, the writing operation will be slowed because the same data should be supplied to "n.sub.1 .times.n.sub.2 " data lines by a special mechanism and because every memory access can write only one pixel.
As mentioned in the above, for simultaneously processing a region of "n.sub.1 .times.n.sub.2 .times.. . . .times.n.sub.k " by a single memory accessing of the multidimensional (two-dimensional or more) memories, the prior art using the high-speed memory device in the time-sharing manner is expensive and requires the time-sharing control mechanism, complicating the device. The prior art using the normal accessing speed memory devices of the number of "n.sub.1 .times.n.sub.2 .times.. . . .times.n.sub.k " to constitute "k"-dimensional memories enlarges the size of the device and requires the address switching mechanism for reading and writing data, complicating the device.